A semiconductor package is used to accommodate at least one integrated circuit component such as semiconductor chip and preferably made compact in size. To achieve this goal, there is a type of small scale semiconductor package, named chip scale package (CSP), which has a size substantially equal or slightly larger than that of the chip incorporated therein.
U.S. Pat. Nos. 5,892,179, 6,103,552, 6,287,893, 6,350,668 and 6,433,427 disclose a CSP structure which directly fabricates build-up layers on a chip and utilizes a RDL (redistribution layer) technique to redistribute bond pads of the chip to predetermined positions, while not requiring a chip carrier such as substrate or lead frame. As shown in FIG. 5, such a CSP structure has a plurality of build-up layers formed on an active surface 100 of the chip 10, including: a dielectric layer 11 disposed over the active surface 100 of the chip 10 and formed with a plurality of vias 110 for exposing bond pads 101 of the chip 10; and a plurality of conductive traces 12 formed on the dielectric layer 11 and electrically connected to the exposed bond pads 101 of the chip 10. A solder mask layer 13 is applied over the conductive traces 12 and formed with a plurality of openings 130, allowing predetermined portions of the conductive traces 12 to be exposed via the openings 130 and bonded to solder balls 14 which serve as input/output (I/O) connections for electrically connecting the chip 10 to an external device such as printed circuit board (not shown). Therefore, the bond pads 101 of the chip 10 are redistributed via the conductive traces 12 to the positions bonded with the solder balls 14 and thus electrically connected to the solder balls 14. In other words, if bond pads formed on a chip are located at peripheral area or arranged by uneven pitches, they can be redistributed using the RDL technique by means of conductive traces to array-arranged positions predetermined for bonding solder balls, and thus a ball grid array or array-arranged solder balls can be subsequently disposed on the predetermined positions to be electrical connected to the bond pads via the conductive traces.
The above CSP structure, however, is defective in that the use of RDL technique or the arrangement of conductive traces is limited in accordance with the chip size or area of the active surface of the chip. Especially with increase in the chip integration and reduction of the chip size, the chip usually cannot provide sufficient surface area for accommodating relatively more solder balls desirably required for the external electrical connection. Accordingly, U.S. Pat. No. 6,271,469 discloses another package structure which forms build-up layers on a chip and provides additional or more surface area for carrying solder balls or I/O connections. As shown in FIG. 6, this package structure uses an encapsulation body 15 to encapsulate a non-active surface 102 and side surfaces 103 of the chip 10, with the active surface 100 of the chip 10 exposed outside and flush with a surface 150 of the encapsulation body 15. A first dielectric layer 16 is applied over the active surface 100 of the chip 10 and the surface 150 of the encapsulation body 15, the first dielectric layer 16 having a plurality of vias 160 formed by a laser drilling technique for exposing the bond pads 101 of the chip 10. A plurality of conductive traces 12 (hereinafter referred to as “first conductive traces”) are formed on the first dielectric layer 16 and electrically connected to the exposed bond pads 101. Then, a second dielectric layer 17 is disposed over the first conductive traces 12 and formed with a plurality of vias 170 for exposing predetermined portions of the first conductive traces 12. A plurality of second conductive traces 18 are formed on the second dielectric layer 17 and electrically connected to the exposed portions of the first conductive traces 12. Finally, the solder mask layer 13 is applied over the second conductive traces 18, allowing predetermined portions of the second conductive traces 18 to be exposed via the openings 130 of the solder mask layer 13 and bonded to the solder balls 14. Therefore, the surface 150 of the encapsulation body 15 that encapsulates the chip 10 provides more surface area than the active surface 100 of the chip 10 and can be mounted with more solder balls 14 for external electrical connection.
However, a significant drawback incurred by the above package structure is that when the laser drilling technique is employed to form vias through the first dielectric layer for exposing the bond pads on the chip, the bond pads covered by the first dielectric layer cannot be easily and precisely recognized by laser in position, making the vias not able to accurately correspond to the positions of the bond pads. As a result, the bond pads on the chip fail to be completely exposed, and electrical connection between the conductive traces and the incompletely-exposed bond pads is degraded, thereby damaging yield and reliability of the fabricated packages. Moreover, the provision of first dielectric layer on the chip and encapsulation body and the use of laser drilling technique would undesirably increase fabrication costs and process complexity. Besides, since the first dielectric layer has a different coefficient of thermal expansion (CTE) from the chip and encapsulation body, under a high temperature environment or in a thermal cycle, delamination may easily occur at interface between the first dielectric layer and the chip or encapsulation body due to different thermal stresses produced therefrom, making the quality and reliability of the fabricated products degraded.
Therefore, the problem to be solved herein is to provide a semiconductor package which can assure electrical connection between conductive traces and bond pads formed on the chip and improve the production yield and reliability of the semiconductor package.